1. Field of the Invention
The present invention relates to a trace controller for tracing on a microprocessor.
2. Description of Related Art
Means to debug a microprocessor involve external tracing on instruction execution state and data access state of the microprocessor. When tracing, a trace controller that is connected to a microprocessor collects data such as program counter (PC) values output from the microprocessor and memory addresses accessed by the microprocessor. Such a trace control method is disclosed in Japanese Unexamined Patent Publication No. 2000-20345, 10-240570 and 6-161818, for example.
On the other hand, means to improve an instruction execution speed of a microprocessor involve pipelining. The pipelining technique executes in parallel stages in a microprocessor, such as instruction fetch (IF), instruction decode (ID), memory access (MEM), and write back (WB), thereby improving a processing speed of the microprocessor. This technique is used in many microprocessors. Further, means to further improve an instruction execution speed of a microprocessor using pipelining involve non-blocking access and reordering access.
The non-blocking access is an operation that, if no dependencies exist between a plurality of load/store instructions to be executed, executes the next instruction without waiting for memory access for the previously executed instruction to be completed. The reordering access is an operation that completes data access cycles regardless of an instruction execution order if no dependencies exist between load/store instructions. For example, if there are a plurality of memory blocks having different memory access speeds, a control bus, address bus and data bus between a microprocessor and each memory block, which are referred to herein collectively as the memory bus, exist independently from each other, thus allowing independent issue of a data access cycle to each memory block. It is therefore possible to issue a data access cycle to a memory block without waiting for a data access cycle for another memory block to be completed.
In a microprocessor that implements the non-blocking access and the reordering access, an order to execute instructions (order to issue data access cycles) and an order to complete data access cycles are not the same in some cases due to a difference in memory access speed. For example, when using two memory blocks with different memory access speeds (high-speed memory and low-speed memory), if the issue of a data access cycle for the low-speed memory precedes the issue of a data access cycle for the high-speed memory, the data access cycle for the high-speed memory can complete earlier than the data access cycle for the low-speed memory in some cases.
A trace operation during execution of load/store instructions in a conventional microprocessor 30 that implements non-blocking access and reordering access and a conventional trace controller 35 is described hereinafter with reference to FIGS. 3 and 4. FIG. 3 shows the configuration of the microprocessor 30 and the trace controller 35.
The configuration of the microprocessor 30 is described first. An execution control section 301 is a circuit that controls the execution of instructions. When a load instruction is executed, the execution control section 301 supplies an execution program counter value (PC), access address (A), R/W information (RW) and access size (S) and, additionally, write data information (WD) in the execution of a store instruction. These pieces of information are collectively referred to herein as the data access information. The data access information is also supplied to an output terminal group 309. The data access information supplied to the output terminal group 309 is collected as trace data by a trace controller 35 and also used as index information to make an association with write-back information that is output from an output terminal group 310, which is described later.
A memory access control section 302 is a circuit that makes data access to high-speed memory 306 and low-speed memory 307. The data access information is supplied from the execution control section 301 to an input selection section 303. The input selection section 303 selects a buffer to store the received data access information from a plurality of buffers, which are four buffers A to D in FIG. 3, in a load/store buffer 304. The load/store buffer 304 includes a plurality of buffers, four buffers A to D in FIG. 3, and stores data access information to the high-speed memory 306 or the low-speed memory 307 and also stores read data (RD) read out from the high-speed memory 306 or the low-speed memory 307 after executing the load instruction.
An output selection section 305 selects the read data RD to be supplied to a write-back control section 308 from the plurality of buffers in the load/store buffer 304. Further, the output selection section 305 supplies the selected read data RD and a PC value (RPC), access address (RA), R/W information (RRW) and read data size (RS), which are data access information corresponding to the selected read data RD, to the output terminal group 310. The pieces of information supplied to the output terminal group 310 are collectively referred to herein as the write-back information.
The write-back control section 308 stores the read data supplied from the memory access control section 302 into a register file, not shown, in the microprocessor 30.
If an instruction to be executed in succession to a load/store instruction is not dependent on the result of the load/store instruction, the microprocessor 30 starts executing the next instruction without waiting for the execution of the load/store instruction to be completed (the non-blocking access). Further, when the data access information is stored in more than one of the buffers A to D in the load/store buffer 304, if no data access cycle is issued to a memory bus of the memory to be accessed and no dependencies exist between the load/store instructions given by the plurality of pieces of data access information, the microprocessor 30 issues data access cycles to a plurality of memory buses in parallel (the reordering access). Therefore, there are cases where the data access cycles are completed in a different order from an instruction execution order.
The configuration of the trace controller 35 is described next. A data access information detection section 351 receives the data access information output from the output terminal group 309 of the microprocessor 30 through an input terminal group 357. The data access information detection section 351 generates and outputs trace information 360 from the received data access information containing PC, A, RW and S, and, additionally, WD in the case of a store instruction. Further, the data access information detection section 351 generates trace control information (TC) and, if the received data access information relates to a load instruction, supplies the generated trace control information TC to an input selection section 352.
The trace control information TC is information that indicates whether to trace the instruction executed in the microprocessor 30, ie, whether to supply the data access information and write-back information detected by the trace controller 35 to an external analysis unit. The trace controller 35 stores the trace control information TC in a trace control buffer 353 and associates the write-back information output after completion of a read data cycle in the microprocessor 30 with the trace control information stored in the trace control buffer 353, thereby determining whether to output the write-back information.
The input selection section 352 receives the trace control information TC and the data access information (PC, A, RW and S) and supplies them to one of a plurality of buffers, which are buffers A to D in FIG. 3, in the trace control buffer 353. In the selection of the buffer to store the information, the input selection section 352 selects the buffer where the trace control information TC is already selected and output by the output selection section 355.
The trace control buffer 353 includes a plurality of buffers, which are the buffers A to D in FIG. 3, and stores the trace control information TC and the data access information supplied from the input selection section 352. The data access information is stored together with the trace control information TC so that a comparison/output control section 354, which is described later, uses the data access information as index information for associating the trace control information TC with the read data information.
The comparison/output control section 354 receives the write-back information (RPC, RA, RRW and RS) that is output from the output terminal group 310 of the microprocessor 30 through an input terminal group 358. The comparison/output control section 354 then compares the received write-back information with the data access information that is stored in the trace control buffer 353 and selects the buffer that stores the data access information corresponding to the write-back information. Further, the comparison/output control section 354 gives an instruction to an output selection section 355 so as to select the trace control information TC that is stored in the selected buffer as the one corresponding to the write-back information.
The output selection section 355 selects the trace control information TC that is stored in the buffer specified by the comparison/output control section 354 and supplies it to a write-back information detection section 356. The write-back information detection section 356 receives write-back information from the microprocessor 30 through the input terminal group 358 and then generates and outputs trace information 361 from the received write-back information (RPC, RA, RRW, RS and RD). The write-back information detection section 356 determines whether to supply the trace information 361 to an external analysis unit or the like according to what is indicated by the trace control information TC.
As described in the foregoing, the trace controller 35 to perform tracing on the microprocessor 30 that implements the non-blocking access and the reordering access use the data access information (PC, A, RW, S) and write-back information (RPC, RA, RRW, RS) as the index information for associating the trace control information TC and the read data RD. The operation for associating the trace control information TC with the read data RD is described hereinafter in detail with reference to FIG. 4.
FIG. 4 shows a case where the microprocessor 30 starts executing a load instruction 1 (LOAD 1), a load instruction 2 (LOAD 2), a load instruction 3 (LOAD 3) and a load instruction 4 (LOAD 4) sequentially. When each load instruction is executed in EX stage, the trace controller 35 receives the data access information and then generates and outputs the trace information 360. The trace control buffers 353A to 353D in FIG. 4 indicate the buffers A to D that are included in the trace control buffer 353. The buffers 353A to 353D respectively store the trace control information TC1 to TC4 that is generated in the data access information detection section 351 and the data access information that is used as index information. FIG. 4 shows a case where the load instructions 1 and 2 are objects of tracing while the load instructions 3 and 4 are excluded from of tracing. Therefore, the trace control information TC1 and TC2 corresponding to the load instructions 1 and 2 is “ON” and the trace control information TC3 and TC4 corresponding to the load instructions 3 and 4 is “OFF”.
Since the microprocessor 30 implements the reordering access, the order to start executing the load instructions 1 to 4 and the order to complete the data access cycles in MEM stage do not always the same. The ends 1 to 4 in FIG. 4 respectively indicate the timing to complete the data access cycles for the load instructions 1 to 4, which is the timing to complete the MEM stage. FIG. 4 shows a case where the data access cycles are completed in the order of the load instructions 1, 3, 4, and 2.
The trace controller 35 associates the write-back information 41 to 44 that is output from the microprocessor 30 in the order of completing the data access cycles with the trace control information TC1 to TC4. First, when the data access cycle for the load instruction 1 is completed, the trace controller 35 receives the write-back information 41 from the microprocessor 30. The comparison/output control section 354 compares the received write-back information 41 with the data access information stored in the buffers 353A to 353D and selects the buffer 353A that stores the data access information for the load instruction 1 corresponding to the write-back information 41. The write-back information detection section 356 determines whether to output the trace information 361 according to the trace control information TC1 that is stored in the selected buffer 353A. The comparison/output control section 354 further makes comparison on the write-back information 42 to 44 in the same manner and determines whether to output the trace information 361 according to the associated trace control information TC.
As described above, the trace method that uses execution PC, access address, R/W information, read data size and so on as index information in the tracing of the load instruction requires storing index information in addition to trace control information, which increases the capacity of the trace control buffer to store the information.